1. Field of the Invention
The present invention relates to an integrated circuit layout structure and method thereof, and more specifically, to an integrated circuit layout structure utilizing auto place and route (APR) layout for reducing an occupied area and improving integration of an integrated circuit and a method thereof.
2. Description of the Prior Art
Standard cells with an identical cell height are used in the conventional auto place and route (APR) layout for an integrated circuit. Each of the standard cells has different functions, but they have the same height. As a result, the standard cells can be integrated for performing different electrical operations. Furthermore, since each of the standard cells has the same height, the standard cells have no difference in height and can be connected as bricks by APR tools, so as to connect a power end and a ground end of each of the standard cells to one another.
Please refer to FIG. 1A, FIG. 1B, and FIG. 1C. FIG. 1A is a diagram of a cell DF 1 and an INV1 3 in the prior art. FIG. 1B is a layout diagram of the cell DF 1 and the INV1 3 in the prior art. FIG. 1C is a layout diagram of a metal layer of the cell DF 1 and the INV1 3 in the prior art. As shown in FIG. 1A to FIG. 1C, the cell DF 1 and the cell INV1 3 have an identical cell height L. Thus, a power end 50 and a ground end 60 of the cell DF 1 are connected to the power end 50 and the ground end 60 of the cell INV1 3 for power transmission when the cell DF 1 and the cell INV1 3 are placed adjacent to each other during layout, respectively.
Please see FIG. 2A, FIG. 2B, and FIG. 2C. FIG. 2A is a diagram of a conventional integrated circuit in the prior art. FIG. 2B is a layout diagram of the conventional integrated circuit in the prior art. FIG. 2C is a metal layer layout diagram of the conventional integrated circuit in the prior art. As shown in FIG. 2A, FIG. 2B and FIG. 2C, the conventional integrated circuit includes the cell DF 1, the cell INV1 3, a cell XOR1 5, a cell NR2 7, a cell AND_3 9, a cell INV2 11, a cell DLYL3 13, and a cell 023ND 15. The cell DF 1, the cell INV1 3, the cell XOR1 5, the cell AND_3 9, the cell INV2 11, the cell DLYL3 13, and the cell 023ND 15 are with the same height L. The cell DF 1, the cell INV1 3, the cell XOR1 5, and the cell NR2 7 are arranged in a first cell row and adjacent by turns. The cell AND_3 9, the cell INV2 11, the cell DLYL3 13, and the cell 023ND 15 are arranged in a second cell row and adjacent in turns. Power ends 50 are disposed on an upper side of the cell DF 1, the cell INV1 3, the cell XOR1 5, and the cell NR2 7 which are located in the first cell row and on a lower side of the cell AND_3 9, the cell INV2 11, the cell DLYL3 13, and the cell 023ND 15 which are located in the second cell row. Ground ends 60 are disposed on a lower side of the cell DF 1, the cell INV1 3, the cell XOR1 5, and the cell NR2 7 which are located in the first cell row and on an upper side of the cell AND_3 9, the cell INV2 11, the cell DLYL3 13, and the cell 023ND 15 which are located in the second cell row, i.e., the ground ends 60 are disposed between the first cell row and the second cell row.
Since cells are required to be connected as bricks according to a method of the conventional integrated circuit layout structure, the cells should have an identical height. Otherwise, power ends or ground ends of the cells cannot transmit power due to discontinuous connection therebetween. Please see FIG. 3A, FIG. 3B, and FIG. 3C. FIG. 3A is a diagram of the cell DF 1 and a cell INV1 2 in the prior art. FIG. 3B is a layout diagram of the cell DF 1 and the cell INV1 2 in the prior art. FIG. 3C is a metal layer layout diagram of the cell DF 1 and the cell INV1 2 in the prior art. As shown in FIG. 3A, FIG. 3B, and FIG. 3C, a cell height L1 of the cell DF 1 is different from a cell height L2 of the cell INV1 2. When the cell DF 1 and the cell INV1 2 are placed in a same row and the ground end 60 of the cell DF 1 is able to be connected to a ground end 60′ of the cell INV1 2, the power end 50 of the cell DF 1 is not able to be connected to a power end 50′ of the cell DF 1 for transmitting power due to a difference in height.
When a cell height of a standard cell integrated by APR layout is required, a cell height of the standard cell is decided by a cell height of the most complicated cell in a whole library in the APR layout system. However, it leads to an increase of an area of the whole integrated circuit and results in waste for a simple cell which is required a small area.